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Quick Link to: PoP Component Drawings

Stack PackageAmkor is offering daisy chain samples of their award winning bottom Package Stackable Very Thin Fine Pitch BGA (PSvfBGA) and their top FBGA optimized for Package on Package (PoP) requirements. PoP has become the solution of choice for an increasing number of mobile consumer applications for 3D integration of logic and memory devices. Amkor’s PSvfBGA is a high density fine pitch BGA package supporting logic or ASIC devices including base band, application and image processors. PoP stacking allows the OEM greater device, supplier and time to market flexibility by sourcing the bottom and top devices from their preferred logic and memory suppliers and then stacking the devices in the PWB surface mount assembly flow. A wide range of leading wireless and mobile integrated device manufacturers are relying on Amkor’s technical and industry leadership in PoP.

For more information, please see Amkor's page.

For recomended 14mm Test Board browse to www.practicalcomponents.com/boards/pc200-pop.htm.

For recomended 12mm Test Board browse to www.practicalcomponents.com/boards/pc200-pop12mm.htm.

Package on Package (PoP) Mating Top and Bottom Daisy Chain Samples
Part Number I/O Count Pitch Body
Size
Ball
Matrix
Ball
Alignment
Quantity
Per Tray
12mm Body Size
A-FBGA128-.65mm-12mm-DC 128 (top) .65mm 12mm 18 x 18 Perimeter TBD
A-PSvfBGA305-.5mm-12mm-DC 305 (bottom) .5mm 12mm 23 x 23 Perimeter TBD
14mm Body Size
A-FBGA152-.65mm-14mm-DC 152 (top) .65mm 14mm 21 x 21 Perimeter TBD
A-PSvfBGA353-.65mm-14mm-DC 353 (bottom) .5mm 14mm 26 x 26 Perimeter TBD

12mm
12mm

14mm
14mm

The top and bottom packages are shipped individually. Customer has to stack the package to
evaluate DC net (A) and (B)

PoP Stack Up

PoP Overall Stack Up Table
FBGA + PSvfBGA Stack
Symbol Unit Min Max Nom
A1 (Ball, 0.5 pitch) mm 0.180 0.280 0.230
A2 (4L laminate) mm 0.260 0.340 0.300
B1 (Ball, 0.65 pitch) mm 0.300 0.360 0.330
B2 (2L laminate) mm 0.160 0.240 0.210
B3 (Mold Cap) mm 0.420 0.480 0.450
Overall Pkg height mm 1.420 1.620 1.520

PSvfBGA Cross Section

  • 10 to 15mm body sizes planned with 12 to 15mm tooled. Additional sizes based on customer demand (please contact Practical for latest availability)
  • Top package I/O interface 0.65mm pitch accommodating 104 to 160 pin counts
  • Fine pitch 0.5mm bottom package footprints
  • Stacked package heights of 1.2mm to 1.6mm available in a variety of configurations (see Stack Up table)
  • Wafer thinning / handling < 100 µm
  • Consistent product performance and reliability
  • Package configurations compliant with JEDEC standards
  • Moisture Resistance Testing is JEDEC Level 3 @ 260 °C
  • Temp Cycle –55/+125 °C, 1000 cycles
  • HAST 130 °C, 85% RH, 96 hours
  • Temp/Humidity 85 °C/85%RH/1000 hours
  • High Temp Storage 150 °C, 1000 hours
  • Board level Thermal Cycle –40/+125 °C, 1000 cycles
  • Available with SAC305 or SAC405 Pb free alloys
  • Parts packages in JEDEC matrix trays

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